Exemplary embodiments of the present invention relate to a semiconductor device and a method for fabricating the same; and, more particularly, to a semiconductor device, which has a floating layer with a portion serving as a guard ring surrounding a cell region, and a method for fabricating the same.
As the design rule of semiconductor devices decreases, there have been difficulties in securing capacitance of capacitors. To secure the capacitance, capacitors with a cylinder structure have been introduced, which may extend an effective area.
To form such cylinder-structure capacitors, a dip-out process is performed. Conventionally, a full dip-out process has been performed to dip out a second region (peripheral circuit region and core region), as well as, a first region (cell region). Due to a step between the first and second regions, however, defects may occur in a contact process, such as a metal contact (M1C) process.
To solve such a problem, a process of dipping out only the first region is applied, instead of the full dip-out process.
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for fabricating a capacitor.
Referring to FIG. 1A, an interlayer dielectric layer 12 is formed on a substrate 11 defining first and second regions 101 and 102. The first region 101 may include a cell region, and the second region 102 may include a peripheral circuit region and a core region.
The interlayer dielectric layer 12 is etched using a storage node contact mask to form a plurality of storage node contact holes, and a plurality of storage node contact plugs (SNC) 13 are formed to be buried in the storage node contact holes and connected to the substrate 11 in the first region 101.
An etch stop layer 14 is formed on a resulting structure, including the SNCs 13, and the isolation layer 15 is formed on the etch stop layer 14.
The isolation layer 15 and the etch stop layer 14 at the first region are sequentially etched using a storage node mask to form a plurality of hole type patterns 16 exposing the SNCs 13.
Referring to FIG. 1B, a conductive layer is deposited over a resulting structure including the patterns 16, and an etch-back process is performed to form a plurality of storage nodes 17 in the respective patterns.
Referring to FIG. 1C, a mask 18 which covers the second region 102 and opens the first region 101 is formed, and a dip-out process 19 using a wet chemical is performed.
Accordingly, the isolation layer 15 is completely removed from the first region, and only the storage nodes 17 remain in the first region. Since the isolation layer 15 at the second region is protected by the mask 18, the isolation layer 15A remains.
In the conventional method, however, when the dip-out process 19 is performed, the wet chemical may permeate (refer to reference numeral 19A) into the second region, such that a bunker (refer to reference numeral B) is formed.
The bunker defect caused by the dip-out process frequently occurs in the guard ring region. The formed bunker, which is a device killing defect, causes a capacitor to fail at a probability of 100%. In a region other than the first region where the dip-out is process is performed, the region is damaged due to a poor guard ring and previous defects during the dip-out process. When M1Cs are formed in a subsequent process, a bridge between the M1Cs may occur causing a capacitor to fail.